NB7V52M - D Flip Flop, 1.8 V / 2.5 V Differential, with Reset and CML Outputs
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool
KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
MC74VHC74 datasheet - Dual D Flip-Flop with Set and Reset. The MC74VHC74
DFF-based CMOS clock divider. | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
High Speed Digital Blocks
Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Figure 1 from High-frequency CML clock dividers in 0.13-/spl mu/m CMOS operating up to 38 GHz | Semantic Scholar
KR100969864B1 - Cml type d flip-flop and frequency divide-by-odd number using the same - Google Patents
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
adding reset function to D Flip FLOP | Forum for Electronics
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
Part 01: Proposal and Overview. Dual Modulus Prescaler Using Current Mode Logic Goals 2.5 GHz Operation 8/9 Dual Modulus 0.18uM BSIM 3 Model. - ppt download
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Circuit configuration of the RTD/HBT MOBILE-based NRZ D-flip flop. | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
ECEN620: Network Theory Broadband Circuit Design Fall 2022
Advantages of Using CMOS - ppt video online download
